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CM8500A
3A BUS TERMINATOR
GENERAL DESCRIPTION
The CM8500A is a switching regulator designed to provide a desired output voltage or termination voltage for various applications by converting voltage supplies ranging from 2.0V to 5.0V. The CM8500A can be implemented to produce regulated output voltages in two different modes. In the default mode, when the VIN/2 pin is open, the output voltage is 50% of the VCCQ. The CM8500A can also be used to produce various user-defined voltages by forcing a voltage on the VIN/2 pin. In this case, the output voltage follows the VIN/2 pin input voltage. The switching regulator is capable of sourcing or sinking up to 3A of current while regulating an output V TT voltage to within 3% or less. The CM8500A, used in conjunction with series termination resistors, provides an excellent voltage source for active termination schemes of high speed transmission lines as those seen in high speed memory buses and distributed backplane designs. The voltage output of the regulator can be used as a termination voltage for other bus interface standards such as SSTL, CMOS, Rambus TM ,GTL+, VME, LV-CMOS, LV-TTL, and PECL. Mother Board PCI / AGP Graphics Game / Play Station Set Top Box IPC SCSI-III Bus terminator Buck Converter
FEATURES
Patent Filed #6,452,366 pin PTSSOP and PSOP package Source and sink up to 3A, no heat sink required Peak Current to 6A Integrated Power MOSFETs Output voltage can be programmed by external resistors Separate voltages for VCCQ and PVDD V OUT of 3% or less at 3A Minimum external components Shutdown for standby or suspend mode operation Thermal shutdown protection 6A Low Noise Current Limit Protection External Soft Start Rail to Rail output Buck Converter
APPLICATIONS
PIN CONFIGURATION
PSOP-16 (PS16)/PTSSOP-16 (PT16) Top View
1 2 3 4 5 6 7 8 VC C2 PV D D 2 VL2 PG N D 2 AG N D VFB VC CQ AG N D 16 15 14 13 12 11 10 9
VCC 1 P V DD1 VL1 PG N D 1 AG N D SD VIN /2 AG SE N
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Champion Microelectronic Corporation
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CM8500A
3A BUS TERMINATOR
PIN DESCRIPTION
Pin No. 1,16 2,15 3,14 Symbol VCC1,VCC2 PVDD1,PVDD2 VL1,VL2 Description Min. Voltage supply for internal circuits Voltage supply for output power transistors Output voltage/inductor connection (IDD1+IDD2, Output RMS current) 4,13 5,9,12 8 6 PGND1,PGND2 AGND Ground for output power transistors Ground for internal reference voltage divider Ground for remote sensing Shutdown active high. CMOS input level 0.75 X VCC 7 10 11 VIN/2 VCCQ VFB Input for external reference voltage Voltage reference for external voltage divider Feedback node for the VTT 0 VCC + 0.3V VIN 5 5 V V V V 2 2 -3 Operating Rating Typ. Max. 2.5 2.5 5 5 3 Unit V V A
AGSEN
SD
BLOCK DIAGRAM
VCCQ 10 VCC1 1 VCC2 16 SD 6 PVDD1 2 PVDD2 15
OSCILLATOR/ RAMP GENERATOR 3 VL1
14
S Q
VL2
100K
ERROR AMP
R + RAMP AMP COMPARATOR Q
VIN/2
7 5 100K
+ -
AGND
AGND
9
20PF
AGND12
8 AGND
11 VFB
4 PGND1
13 PGND2
ORDERING INFORMATION
Part Number CM8500AIT CM8500AIS CM8500AGIT* CM8500AGIS* CM8500ATEVAL *Note: G : Suffix for Pb Free Product Temperature Range -40 to 85 -40 to 85 -40 to 85 -40 to 85 16-Pin 16-Pin 16-Pin 16-Pin Package PTSSOP (PT16) PSOP (PS16) PTSSOP (PT16) PSOP (PS16)
Evaluation Board (T16)
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Champion Microelectronic Corporation
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CM8500A
3A BUS TERMINATOR
ABSOLUTE MAXIMUM RATINGS
Absolute maximum ratings are those values beyond which the device could be permanently damaged. PVDD/VCC/VCCQ ................................................-0.3V to 6.0V Voltage on Any Other Pin ............ GND - 0.3V to VCC + 0.3V Output RMS Current, Source or Sink ...............................3.0A Junction Temperature ........................... ...............150C Storage Temperature ............................. -65C to 125C
Lead Temperature (Soldering, 5 sec)....................... 260C Thermal Resistance(JA )..... ............................... .40C/W
OPERATING CONDITIONS
Temperature Range ............................. -40C to 85C PVDD Operating Range .........................2.0V to 5.0V
(Unless otherwise stated, these specifications apply TA=25C; VCC=+3.3V and PVDD=+3.3V) maximum ratings are stress ratings only and functional device operation is not implied.(Note 1) CM8500A Min. 1.12 1.22 1.32 1.09 1.19 1.28 1.139 1.238 1.337 480 Typ. 1.15 1.25 1.35 1.15 1.25 1.35 1.15 1.25 1.35 50 660 3 6 6 150 180 Max. 1.18 1.28 1.38 1.21 1.31 1.42 1.162 1.263 1.364
ELECTRICAL
CHARACTERISTICS
Symbol SWITCHING REGULATOR
Parameter
Test Conditions
Unit
IOUT = 0, VCCQ = 2.3V VIN/2 = open Note 2 VL Output Voltage, SSTL_2 IOUT = 3A, VIN/2 = open Note 3 VIN/2 ZIN fsw IOUT(RMS) IOUT(PEAK) Ilimit MOSFETs RDS(ON) SUPPLY IVCCA IPVDD Quiescent Current VFB = 1.4V LC unconnected VFB = 1.4V LC unconnected Drain to Source on-State Resistance PVDD=5V Internal Resistor Divider VIN/2 Reference Pin Input Impedance Switching Frequency Maximum Output RMS Current Maximum Output Peak Current Current limit IOUT = 0 Note 2 Note 2 VCCQ = 2.3V VCCQ = 2.5V VCCQ = 2.7V VCCQ = 0 VCCQ = 2.7V VCCQ = 2.5V VCCQ = 2.7V VCCQ = 2.3V VCCQ = 2.5V
V V V V V V V V V K KHz A A A m
CM8500A CM8500A CM8500A CM8500A
200 500
A A
Note 1: Limits are guaranteed by 100% testing, sampling, or correlation with worst case test conditions Note 2: VCC, PVDD = 3.3V 10% Note 3: It's not 100% test
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Champion Microelectronic Corporation
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CM8500A
3A BUS TERMINATOR
FUNCTIONAL DESCRIPTION
The CM8500A is a switching regulator that is capable of sinking and sourcing 3A of current without an external heat sink. CM8500A uses a standard surface mount PTSSOP
Low Noise Current Limit:
CM3708A's current limit is a low noise current limit. It increase the system loop noise immunity while it is doing the current limit protection for the system. The current limit is around 6A for the normal 3A operation.
and PSOP package with bottom metal exposed and the heat can be piped through the bottom of the device and onto the PCB.
INPUTS
The CM8500A integrates power MOSFETs that are capable of source and sink 3A of current while maintaining excellent voltage regulation. The output voltage can be regulated within 3% or less by using the external feedback. Separate voltage supply inputs have been added to fit applications with various power supplies for the databus and power buses. The input voltage pins (VCCQ or VIN/2) determine the output voltages (VL1 or VL2). In the default mode, when the VIN/2 pin is open, the output voltage is 50% of the VCCQ input. If a specific voltage is forced at the VIN/2 pin, the output voltage follows the voltage at the VIN/2 pin. VCCQ suggested connecting to VCCQ of memory module for better tracking with memory VCCQ. VREF The reference voltage could be ranged from 0V to VIN.
OTHER SUPPLY VOLTAGES
Several inputs are provided for the supply voltages: PVDD1, PVDD2, VCC1, and VCC2.
OUPUTS
The output voltage pins (VL1, VL2) are tied to the databus,
address, or clock lines via an external inductor. Output voltage The PVDD1 and PVDD2 provide the power supply to the power is determined by the VCCQ or VIN/2 inputs so it can be from 0V to VIN.. MOSFETs. VCC1 and VCC2 provide the voltage supply to the logic section and internal error amplifiers.
Internal Power Switches:
CM3708A has been integrated 2 Power MOSFETs whose RDS(ON) is around 100m Ohm each.
FEEDBACK
The VFB pin is an input that can be used for closed loop compensation. This input is derived from the voltage output. AGSEN pin is a contact node of internal resistor divider for remote sense.
APPLICATIONS
USING THE CM8500A FOR SSTL BUS TERMINATION
Figure 1 is the typical schematic of the CM8500ATEVAL that shows the recommended approach for bus terminating solutions for SSTL-2 bus. This circuit can be used in PC memory and Graphics memory applications as shown in Figure 2 and Figure 3. Figure 4 shows the PCB layout of the CM8500ATEVAL. Table 1details the key parameters of SSTL_2 specification. Figure 5 shows two different approach of SSTL_2 Terminated Output. (Refer to page 8 for detail description.)
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Champion Microelectronic Corporation
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CM8500A
3A BUS TERMINATOR
APPLICATION CIRCUIT
NOTE:
J3:referance output provided from Vtt J4:short :Demo kit on . open:off(into shutdown mode) J6:reference output provided from shunt regulator
Vref -OUT J3 1 2 5
J5:pin1 ,pin2 short:Vtt = 1/2Vcc
C13 104 1
When external voltage applied ,pin1,2 should be open
R8 100
and pin2:connect to external voltage (+) pin3:connect to external voltage (-) Vtt=1/2 external voltage
D6
TP1 BNC
4 3 L1 3.3uH
100uf /6.3V
100uf /6.3V 820uf /6.3V
SK12
R6,R7(option circuit)forVttVOLTAGEADJUST Vtt=(Vcc*R6)/R6+R7
2
VTT J1
1 2
C12 C3 104
C11
C7 C2 104 C15 10uf /6.3V VDD
D5 SK12 VCC U1 CM8500A 1 2 2 C14 100uf /6.3V R5 100k C4 104 3 4 5 6 J4ON/OFF 2 R6 10k 1 R7 10k 1 2 7 C6 8 102 VCC1 VDD1 VL1 VCC2 VDD2 VL2 16 VDD 15 C16 14 13 12 11 10 9 2 J5 3 1 C5 104 C1 104 C9 100uf /6.3V C10 10uf /6.3V 470uf /6.3V VCC R1 5R1 VDD J2 DC-INPUT 1 2
PGND1 PGND2 AGND1 AGND4 SD 2/VCC FB VCCQ
1
G-sense AGND3
IN/EXT
R3 200k 1 2
1 R4 1k
2 C8 102
Figure 1 . CM8500A Typical Application (Schematic of CM8500A TEVAL)
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Champion Microelectronic Corporation
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CM8500A
3A BUS TERMINATOR
Figure 2. Termination Solution for PC Main Memory (Mother Boards)
Figure 3. Termination Solution for Graphic Memory (AGP Graphics)
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Champion Microelectronic Corporation
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CM8500A
3A BUS TERMINATOR
CM8500ATEVAL PART LIST
Item 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 Q'ty Description Resistors 0805, 5, 1/8W 1 0805, 100, 1/8W 1 0805, 470, 1/8W 1 0805, 1K, 1/8W 1 0805, 100K, 1/8W 2 Capacitors 1 0805, 1nF/ 16V (102) 6 0805, 0.1F/ 16V (104) 1 0805, 1F/ 16V (105) CE 10, 820uF/ 6.3V 1 2 B Size, Tant 10uF/ 6.3V 4 D Size, Tant 100uF/ 6.3V Magnetics 1 3.3uH 5A Inductor IC's 1 CM8500AIT 1 CM431L Connectors 1 2-pin, 2.54mm 4 2-pin Jumper, 2.54mm 1 3-pin Jumper, 2.54mm PCBs 1 CM8500ATEVAL PCB Designator R1 R8 R9 (option) R4 R3, R5 C6, C8 C1, C2, C3, C4, C5 C13 C7 C10, C15 C9, C11, C12, C14 L1 U1 U2 (option) J2 J1, J3, J4, J6 (option) J5 Champion Microelectronic Corp. Manufacturer
Sanyo OSCON
Bipolar Electronic Corp. Champion Microelectronic Corp. Champion Microelectronic Corp.
Vendor Information Bipolar Electronic Corp. Sanyo Phn: +886-3-360 8892
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Champion Microelectronic Corporation
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CM8500A
3A BUS TERMINATOR
CM8500ATEVAL PCB LAYOUT
Figure 4. CM8500AEVAL PCB Layout
SSTL-2 SPECIFICATIONS
SYMBOL VDD VDDQ VREF VTT VIH (DC) VIL (DC) VIH (AC) VIL (AC) IOH (DC) IOL (DC) Notes: PARAMETER Device Supply Voltage Output Supply Voltage Input Reference Voltage Termination Voltage DC Input Logic High DC Input Logic Low AC Input Logic High AC Input Logic Low Output Minimum Source DC Current Output Minimum Sink DC Current - 15.2 15.2 MIN VDDQ 2.3 1.15 VREF - 0.04 VREF + 0.18 - 0.3 VREF + 0.35 VREF - 0.35 2.5 1.25 VREF TYP MAX N/A 2.7 1.35 VREF + 0.04 VDDQ + 0.3 VREF - 0.18 UNITS V V V V V V V V mA mA
INPUT DC LOGIC LEVELS
INPUT AC LOGIC LEVELS
OUTPUT DC CURRENT DRIVE
VREF and VTT must track variations in VDDQ Peak-to-peak AC noise on VREF may not exceed 2% VREF (DC) VTT of transmitting device must track VREF of receiving device
Table 1. Key Specifications for SSTL_2
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Champion Microelectronic Corporation
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CM8500A
3A BUS TERMINATOR
SSTL_2 TERMINATED OUTPUT
Single Terminated Output
Double Terminated Output
Figure 5. SSTL_2 Terminated Output
Note.
The SSTL_2 specification requires adequate output current drive so that parallel termination schemes can be used. The use of parallel termination is important for high-speed signaling, since it allows proper termination of the bus transmission lines, which reduces signal reflections. The result will be improved settling, lower EMI emissions, and higher possible clock rates. A minimumtermination resistance of 23 to VTT can be used and still comply with the minimum output voltages and output currents of theSSTL_2 specification.
Two choices for implementing the parallel termination are shown in Figure 5.
Double Terminated Output
The bus is terminated at both ends with a 50 resistor, for a combined parallel resistance of 25.
Single Terminated Output
The bus is terminated at the far end from the controller with a single 25 resistor. It is strongly recommended that the single resistor termination scheme be used for best performance. The benefits of this approach include reduced cost, simpler signal routing, reduced reflections, and better signal bandwidth and settling.
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Champion Microelectronic Corporation
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CM8500A
3A BUS TERMINATOR
CM8500AEVAL TESTING DIAGRAM
Figure 6. CM8500AEVAL Typical Testing Diagram
TYPICAL CHARACTERISTICS
CM8500 Temperature vs. VTT (VCC,VCCQ&VDD=3.3V) 1.350 1.300 VTT(V) 1.250 1.200 1.150 -40 -30 -20 -10 0 10 20 30 T( ) 40 50 60 70 80 85
1A 2A 3A
Temperature vs. VTT VCC, VCCQ & VDD=3.3V
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Champion Microelectronic Corporation
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CM8500A
3A BUS TERMINATOR
CM8500 Temperature vs. VTT (VCC,VCCQ&VDD=2.5V) 1.350 1.300 VTT(V) 1.250 1.200 1.150 -40 -30 -20 -10 0 10 20 30 T( ) 40 50 60 70 80 85 1A 2A 3A
Temperature vs. VTT VCC, VCCQ & VDD=2.5V
2V INPUT
LOAD: 0A - 3A
2V INPUT
LOAD: 3A - 0A
2.5V INPUT
LOAD: 0A - 3A
2.5V INPUT
LOAD: 3A - 0A
3.3V INPUT
LOAD: 0A - 3A
3.3V INPUT
LOAD: 3A - 0A
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Champion Microelectronic Corporation
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CM8500A
3A BUS TERMINATOR
PACKAGE DIMENSION
16-PIN PTSSOP (PT16)
16-PIN PSOP (PS16)
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Champion Microelectronic Corporation
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CM8500A
3A BUS TERMINATOR
IMPORTANT NOTICE
Champion Microelectronic Corporation (CMC) reserves the right to make changes to its products or to discontinue any integrated circuit product or service without notice, and advises its customers to obtain the latest version of relevant information to verify, before placing orders, that the information being relied on is current. A few applications using integrated circuit products may involve potential risks of death, personal injury, or severe property or environmental damage. CMC integrated circuit products are not designed, intended, authorized, or warranted to be suitable for use in life-support applications, devices or systems or other critical applications. provide Use of CMC products in such applications is understood to be fully at the risk of the customer. with the customer's applications, the customer should design and operating safeguards. In order to minimize risks associated adequate
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